In mainframe computer multi-processor packaging designs, subassemblies containing a fraction of the total system processors are interconnected to allow direct communication and sharing of resources (e.g., memory) between all system processors.
Testing of data and communication paths within a subassembly (internal communication paths) to their interface with external paths often requires a full system's complement of subassemblies in order to exercise all of the paths. For example, a system with 8 subassemblies would require all 8 subassemblies to be interconnected to test all of the communication and data paths. Starting a test with all 8 subassemblies previously untested creates an exposure to having multiple subassemblies failing. In addition, this situation results in considerable failure isolation activity and time to determine which subassemblies are working versus which subassemblies are failing.
An alternative process may start with 7 tested subassemblies and one untested subassembly installed in a system. The untested subassembly (tester) would be the target of the test. However, this strategy drives additional inventory in setting up a system with 7 good, tested subassemblies. For example, if a manufacturing line required 20 testers, 140 known good subassemblies would need to be held captive for these testers. If subassemblies cost, for example $30,000 each, then the cost of the inventory held captive would be $4,200,000.
Another alternative process may be to design circuit cards (wrap cards) that simulate a processor subassembly by connecting communication input paths to communication output paths. In the example above using 8 subassemblies, 7 design circuit cards would be needed to account for the differences at each subassembly plug location. Also, each of the 7 design circuit cards would need to be plugged in each tester. This is a costly solution in the design, release, and manufacture of 7 cards per untested subassembly (tester).